A flip chip microelectronic assembly includes a direct electrical connection of facing-down (that is, “flipped”) electronic components onto substrates, such as ceramic substrates, circuit boards, or carriers using conductive bump bond pads of the chip. Flip chip technology is quickly replacing older wire bonding technology that uses facing-up chips with a wire connected to each pad on the chip.
The flip chip components used in flip chip microelectronic assemblies are predominantly semiconductor devices, however, components such as passive filters, detector arrays, and memory devices are also being used in flip chip form. Flip chips are advantageous because of their high-speed electrical performance when compared to other assembly methods. Eliminating bond wires reduces the delay in inductance and capacitance of the connection, and substantially shortens the current path, resulting in a high-speed off-chip interconnection.
Flip chips also provide the most rugged mechanical interconnection. When underfilled with an adhesive such as an epoxy, flip chips can withstand the most rugged durability testing. Additionally, flip chips can be the lowest cost interconnection for high-volume automated production.
Flip chips are typically made by placing solder bumps on a silicon chip, and the solder bump flip chip process typically includes four sequential steps: 1) preparing the chip for solder bumping; 2) forming or placing the solder bumps on the chip; 3) attaching the solder bumped chip to a board, substrate or carrier; and 4) completing the assembly with an adhesive underfill. The bumps of the flip chip assembly serve several functions. The bumps provide electrical conductive paths from the chip (or die) to the substrate on which the chip is mounted. A thermally conductive path is also provided by the bumps to carry heat from the chip to the substrate. The bumps also provide part of the mechanical mounting of the chip to the substrate. Finally, the bumps act as a short lead to relieve mechanical strain between the chip and the substrate.
Eutectic solder material containing lead (Pb) and tin (Sn) is typically used for solder bumps. A commonly used lead containing eutectic solder has about 63% tin (Sb) and 37% lead (Pb). This combination gives the solder material suitable melting point and low electrical resistivity.
Lead is a toxic material. Legislation and industry requirements have demanded lead-free solder bumps. Companies in the supply chain of the electronics interconnection industry are actively seeking to replace Sn—Pb solder. However, the commonly known lead-free solder, such as Sn—Ag, Sn—Ag—Cu and their inter-metallic components are too brittle, therefore, suffering cracking. On the other hand, high-lead bumps are also preferred by the industry for applying in high electro-migration performance. Addition of lead provides increased corrosion resistance, lowers the reflow temperature of pure tin, and lowers the surface tension of pure tin. High-lead bumps are also brittle and each prone to cracking.
Bump cracking is typically generated by stress. The coefficient of thermal expansion (CTE) mismatch between materials in the package assembly is one of the main reasons causing stress. For example, silicon substrate typically has a CTE of higher than about 3 ppm/C, low-k dielectric has a CTE of higher than about 20 ppm/C, while the package substrate has a CTE of higher than about 17 ppm/C. The significant difference of CTEs introduces stress to the structure when thermal change occurs. One solution to this problem is through the underfill process in which a liquid epoxy is dispensed along one or two sides of a chip to fill the gap between the chip and a substrate. Epoxy underfill helps spread the stress and protect the solder bumps.
With low-k dielectrics widely used in the integrated circuit, a dilemma exists between the protection of bumps and low-k dielectrics. The protection of brittle bumps demands high strength underfills. However, the low-k dielectrics may be harmed by high strength underfill material and problems such as delaminating occur.
Therefore, with low-k dielectrics used, both lead-free and high-lead bumps need to be protected, preferably without using high strength underfill. Conventional solutions for the bump cracking problem have been concentrated on materials. Exploring a solution from a view of the structure therefore becomes valuable. The preferred embodiment of the present invention provides a solution with a modified structure.